Figure illustrates single bus organization of the data paths inside the CPU.

• ALU and all CPU registers are connected through a common bus. Different than the external bus
• MAR (Memory Address Register) MDR (Memory Data Register) used to communicate with the main memory through Address and Data bus
• The registers R0 to Rn-1 are general purpose registers but some of them can be used as Index registers and Stack pointer
• Registers Y and Z are used only by the CPU for temporary storage during execution of some instructions. They never used for storing the data generated by one instruction for later use by another Instruction

Execution in Single Bus Organization

Most of the CPU operations in Fetch and Execution phase can be carried out by performing one or more of the following functions in some pre-specified sequence.

1. Fetching a word from the memory
2. Storing a Word into the Memory
3. Register Transfers
4. Performing an Arithmetic or Logic Operation

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